NXP Semiconductors /MIMXRT1021 /IOMUXC /SW_MUX_CTL_PAD_GPIO_AD_B0_12

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Interpret as SW_MUX_CTL_PAD_GPIO_AD_B0_12

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

MUX_MODE=ALT0, SION=DISABLED

Description

SW_MUX_CTL_PAD_GPIO_AD_B0_12 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: ENET_RX_ER of instance: enet

1 (ALT1): Select mux mode: ALT1 mux port: LPSPI1_SDO of instance: lpspi1

2 (ALT2): Select mux mode: ALT2 mux port: LPUART3_CTS_B of instance: lpuart3

3 (ALT3): Select mux mode: ALT3 mux port: KPP_COL02 of instance: kpp

4 (ALT4): Select mux mode: ALT4 mux port: FLEXPWM2_PWMA01 of instance: flexpwm2

5 (ALT5): Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1

6 (ALT6): Select mux mode: ALT6 mux port: ARM_CM7_TRACE00 of instance: cm7_mxrt

7 (ALT7): Select mux mode: ALT7 mux port: SNVS_HP_VIO_5_CTL of instance: snvs_hp

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_AD_B0_12

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